1. Field of the Invention
The present invention relates to a semiconductor device for measuring an overlay error, a method for measuring an overlay error, a lithographic apparatus and a method for manufacturing a device.
2. Description of the Related Art
A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning” direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
An integrated circuit is formed of a plurality of individual layers which are each patterned according to its specific pattern as explained above. Each patterned layer must have a certain alignment or overlay with the previous patterned layer(s) on which the layer is located to ensure that an integrated circuit according to the design can be formed. For this reason, lithographic processing requires that all patterns are aligned with respect to each other. A measure for the accuracy of the alignment is the overlay between successive patterns, i.e., one pattern superimposed on a preceding created pattern. The mismatch in overlay is commonly referred to as an overlay error.
Overlay can be measured optically by overlay markers which comprise one part that is created in a first layer during a first patterning and another part that is created in a successive layer during a subsequent patterning. The relative position of the two parts is used as a measure for the overlay. This procedure can be repeated as many times as required during the production stage of the integrated circuit.
Also, overlay can be measured after completion of the production stage of the integrated circuit by electrical measurements which basically correlate yield to overlay. Such electrical measurements typically provide simple Boolean results, i.e., a short exists between two layers or not. Typically, the prior art applies electrical measurements on arrays of structures with various known displacements that create shorts or opens when a specific overlay error is reached. All structures are measured and the breaking point between working/not working determines the overlay. The overlay error cannot be determined with a precision smaller than the built-in displacement. The drawback of this way of working is that fine-grained measurement requires a large amount of structures and measurements.